The present invention relates to integrated circuit devices and, more particularly, to flash memory devices and programming methods thereof.
A variety of applications have been developed wherein it is desirable to utilize an integrated circuit (semiconductor) memory device that is electrically erasable and programmable but which does not require a refresh of stored data. Research has further been directed to providing an increased storage capacitance and integrity of data storage in such non-volatile memory devices. One example of non-volatile memory devices that may provide large capacity and high data integrity without refresh of the stored data is a NAND-type flash memory device. Because data is maintained even when power is turned off, such flash memory devices have been widely used in a variety of electronic devices (e.g., hand held terminals, portable computers etc.) where these is a risk of an unexpected power loss (such as from an operator turning off the device).
Non-volatile semiconductor memory devices, such as the NAND flash memory device, may include electrically erasable and programmable memories cells that, under ordinary usage act as read-only memory cells. These devices are sometimes referred to as Flash Electrically Erasable Programmable Read Only Memory cells (“Flash EEPROM cells”). A flash memory cell typically includes a cell transistor. The cell transistor may include a semiconductor substrate (or bulk) of a first-conductivity-type (e.g., P-type) and spaced apart source and drain regions of a second-conductivity-type (e.g., N-type). A floating gate is located between the source and drain regions and stores a charge and a control gate is located on the floating gate. A conventional memory cell array including flash EEPROM cells with such a structure is illustrated in FIG. 1.
As illustrated in FIG. 1, a memory cell array 1 includes a plurality of cell strings (or NAND strings) 10 respectively corresponding to bit lines BL0–BLn. Each of the cell strings 10 includes a string selection transistor SST as a first selection transistor, a ground selection transistor GST as a second selection transistor and a plurality of flash EEPROM cells M0–Mm serially connected between the selection transistors SST and GST. The string selection transistor SST has a drain connected to a corresponding bit line and a gate connected to a string selection line SSL. The ground selection transistor GST has a source connected to a source column selection line CSL and a gate connected to a ground selection line GSL. The flash EEPORM cells M0–Mm are serially connected between a source of the string selection transistor and a drain of the ground selection transistor GSL. The cells M0–Mm are connected to corresponding word lines WL0–WLm, respectively. The word lines WL0–WLm are connected to the string selection line SSL and the ground selection line GSL is connected to a row decoder circuit (X-DEC) 2.
FIG. 2 is a timing diagram schematically illustrating a programming operation for a conventional flash memory device such as that illustrated in FIG. 1. Such a device is described in U.S. Pat. No. 6,353,555 entitled “FLASH MEMORY DEVICE CAPABLE OF MINIMIZING A SUBSTRATE VOLTAGE BOUNCING AND A PROGRAM METHOD THEREOF”. As shown in FIG. 2, a program cycle is divided into a bit line setup period, a program period, a recovery (or discharge) period and a verification period. Before the bit line setup period, the bit lines BL0–BLn may be precharged to a power voltage or a ground voltage in the bit line setup section in accordance with program data loaded for example, to a page buffer circuit. In other words, program data such as a “0” for cells to be programmed and a “1” for cells to be program-inhibited may be loaded. For instance, a bit line that is connected to an EEPORM cell transistor to be programmed may be precharged to the ground voltage (VSS). A bit line that is connected to an EEPORM cell transistor inhibited from being programmed may be precharged to the power voltage (VCC). In addition, in the bit line setup period, the string selection line SSL is at the power voltage and the ground selection line GSL and the word lines WL0–WLm are at the ground voltage.
In the program period, a selected word line is set to a program voltage Vpgm (e.g., 15.5V–20V), and non-selected word lines are set up to a pass voltage Vpass (e.g., 10V). For the EEPROM cell transistors connected to bit lines at the ground voltage a bias condition allowing Fowler-Nordheim tunneling (F-N tunneling) is satisfied and electrons are provided to program a floating gate of the EEPROM cell transistor from a bulk electron source/sink where a channel is formed (drain side). In contrast, EEPROM cell transistors connected to bit lines at the power voltage (VCC) are program-inhibited. Before determining whether the EEPROM cell transistor has a required target threshold voltage, voltages on word lines and bit lines may be discharged to the ground voltage as shown during the recovery period (i.e., the discharging period) of FIG. 2.
Examples of program inhibit operations are described in U.S. Pat. No. 5,677,873 entitled “METHOD OF PROGRAMMING FLASH EEPROM INTERGRATED CIRCUIT MEMORY DEVICES TO PREVENT INADVERTENT PROGRAMMING OF NONDESIGNATED NAND MEMORY CELLS THEREIN” and in U.S. Pat. No. 5,991,202 entitled “METHOD FOR REDUCING PROGRAM DISTURB DURING SELF-BOOSTING IN A NAND FALSH MEMORY,” the disclosures of which are incorporated herein by reference as if set forth in their entirety.
As described above, a high program voltage Vpgm is applied to the selected word line during the program period of the programming cycle. For the selected word line, a required time for setting a control gate voltage of each flash EEPORM cell to the program voltage typically varies depending on its separation from the row decoder circuit 2. In other words, a first time (in FIG. 2, marked by “A”) is shorter than a second time (in FIG. 2, marked by “B”), wherein the first time A is a time needed to set a control gate voltage of a cell close to the row decoder circuit 2 to the program voltage and the second time B is the time needed to set a control gate voltage of a cell far away from the row decoder circuit 2 to the program voltage. This is generally a result of placement of a control gate load of a cell farther away from the row decoder circuit 2 for cells that are farther away from row decoder circuit 2.
Thus, as shown in FIG. 2, in cell(s) far away the row decoder circuit 2, a time that the program voltage is applied relatively short in comparison with cell(s) close to the row decoder circuit 2. In other words, a threshold voltage distribution becomes wider than would otherwise be the case due to a spaced distance from the row decoder circuit 2 for various cells. As a result, an increased programming time is generally provided to ensure programming of flash EEPROM cells far away the row decoder circuit 2 to a target threshold voltage. As a result, a programming time for the memory device increases. Furthermore, as an increased time is provided for programming cell(s) far away the row decoder circuit 2, a threshold voltage of cell(s) close to the row decoder circuit 2 may become higher. If the threshold voltage of a cell is higher than the target threshold voltage, a higher read voltage should generally be applied to a word line of this cell in a read operation. The increase of the read voltage may cause a soft write phenomenon, where electrons are input to a floating gate of a cell transistor by a tunnel effect. As a result, the higher the voltage applied to non-selected word lines in a read operation, the worse a read retention characteristic of the flash EEPORM cell (referred to as data retention characteristic) may become. A difference in threshold voltage, thus, may cause an increase of program time and deterioration of a read retention characteristic of the memory device.